Tegra boards feature a NS16550-compatible serial mapped into the MMIO
space. Add support for its use both as a full-featured serial port and
as an earlyprintk driver.

This patch adds a quirk for platforms, such as the Tegra, which require
require the NS16550 Rx timeout interrupt to be enabled for receive to
function properly. The same quirk is applied in the eqvuialent Linux
driver [1].

This quirk is selectively enabled for the platform using a new "hw_quirks"
member with a corresponding set of bitmasks.  The existing quirk,
dw_usr_bsy was updated to match this approach as well.

[1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=4539c24fe4f92c09ee668ef959d3e8180df619b9

Signed-off-by: Kyle Temkin <[email protected]>
Signed-off-by: Chris Patterson <[email protected]>

…e tree

Currently, the interrupt parent is left undefined during creation in
make_gic_node().  In cases where a non-GIC interrupt controller is present,
this can lead to incorrect assignment of interrupt parents.

On the Tegra, the gic's interrupt parent is set to itself:

	gic: interrupt-controller@0,50041000 {
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x50041000 0x0 0x1000>,
		      <0x0 0x50042000 0x0 0x2000>,
		      <0x0 0x50044000 0x0 0x2000>,
		      <0x0 0x50046000 0x0 0x2000>;
		interrupts = <GIC_PPI 9
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		interrupt-parent = <&gic>;
	};

To prevent the hardware domain from assuming the Legacy Interrupt Controller
(lic) as the GIC's interrupt-parent, this change explicitly assigns
the interrupt-parent property from the host device tree.

Authored-by: Kyle Temkin <[email protected]>
Signed-off-by: Kyle Temkin <[email protected]>
Signed-off-by: Chris Patterson <[email protected]>
Reviewed-by: Stefano Stabellini <[email protected]>

Some common platforms (e.g. Tegra) have non-traditional IRQ controllers
that must be programmed in addition to their primary GICs-- and which
can come in unusual topologies. Device trees for targets that feature
these controllers often deviate from the conventions that Xen expects.

This commit provides a foundation for support of these platforms, by
allowing the platform to decide which IRQs can be routed by Xen, rather
than assuming that only GIC-connected IRQs can be routed.  This enables
platform specific logic to routing the IRQ to Xen and Guest.

As dt_irq_translate() is presently hard-coded to just support the
primary interrupt controller, instead rely on the newly added
platform_irq_is_routable() check instead.  The default behaviour of this
new function should be consistent with the previous checks for platforms
that do not implement it.

Authored-by: Kyle Temkin <[email protected]>
Signed-off-by: Kyle Temkin <[email protected]>
Signed-off-by: Chris Patterson <[email protected]>

Tegra devices have a legacy interrupt controller (lic, or ictlr) that
must be programmed in parallel with their primary GIC. For all intents
and purposes, we treat these devices attached to this controller as
connected to the primary GIC, as it will be handling their interrupts.

This commit adds support for exposing the ictlr to the hardware domain;
but a future commit will extend this to support exposing a virtualized
version of the ictlr to the hardware domain, and to ensure that
interrupts are unmasked properly when routed to a Xen, or to a domain
other than the hardware domain.

Authored-by: Kyle Temkin <[email protected]>
Signed-off-by: Kyle Temkin <[email protected]>
Signed-off-by: Chris Patterson <[email protected]>

The addition of new IRQ-related platform hooks now allow platforms to
perform platform-specific interrupt logic, such as allowing virtualization
of platform-specific interrupt controller hardware.

This commit adds the ability for the platform to identify the domain
a given IRQ is routed to, allowing platform logic to deny access to
registers associated with a given IRQ unless the requesting domain
'owns' the IRQ. This will be used on Tegra platforms, where the hardware
domain needs access to its legacy interrupt controller, but should not
be able to control registers that correspond to other domains' IRQs, or
sections associated with IRQs routed to Xen.

Authored-by: Kyle Temkin <[email protected]>
Signed-off-by: Kyle Temkin <[email protected]>
Signed-off-by: Chris Patterson <[email protected]>
Reviewed-by: Stefano Stabellini <[email protected]>

…terrupts

Several Tegra hardware devices, and the Tegra device tree, expect
the presence of a Tegra Legacy Interrupt Controller (LIC) in the hardware
domain. Accordingly, we'll need to expose (most of) the LIC's registers
to the hardware domain.

As the Tegra LIC provides the ability to modify interrupt delivery (e.g.
by masking interrupts, forcing asserting/clearing them, or adjusting
their prority), it's important that the hardware domain's access be
mediated. This commit adds read/write handlers that prohibit
modification of register sections corresponding to interrupts not owned
by the hardware domain.

Note that this is written to be domain agnostic; this allows the
potential to e.g. map the ictlr into multiple domains if this is desired
for passthrough in the future.

Authored-by: Kyle Temkin <[email protected]>
Signed-off-by: Kyle Temkin <[email protected]>
Signed-off-by: Chris Patterson <[email protected]>